
SBT = sbt


# Generate Verilog code
default:
	$(SBT)  "runMain MACArray.MACMain"

mac-test:
	$(SBT) "testOnly MYMAC.MACTester"

mac-test-vcd:
	$(SBT) "testOnly MYMAC.MACTester -- -DwriteVcd=1"	

##	sbt run

# Run the test
test:
	sbt test

clean:
	git clean -fd

